1. Field of the Invention
The present invention relates to a semiconductor memory device having a so-called redundancy repair circuit for repairing a defect in a memory cell.
2. Description of the Prior Art
In recent years, as a data capacity has become larger in the field of digital equipment represented by a high-vision television set, a semiconductor memory has become larger in capacity, and higher in the degree of integration due to the fine design rules thereof. On the other hand, as the memory has thus become larger in capacity, and higher in the degree of integration due to the fine design rules thereof, the probability of the occurrence of defective memory cells has tended to increase. The defective memory cells cause a reduction in chip fabrication yield. Accordingly, it is general practice to provide a semiconductor memory device with a so-called redundancy repair circuit which improves the chip fabrication yield by circuit-wise repairing the defective memory cells causing the reduced chip fabrication yield using preliminarily mounted redundant memory cells.
An example of such a semiconductor memory device is described in, e.g., Japanese Laid-Open Patent Publication No. 2005-71413 (the publication will be hereinafter referred to as Patent Document 1). The semiconductor memory device includes a plurality of memory cell blocks, first fuse blocks, second fuse blocks, a plurality of selection circuits, a plurality of first determination circuits, and a plurality of second determination circuits. Each of the memory cell blocks is composed of memory cells arranged in rows and columns. The first fuse blocks are disposed for the individual memory cell blocks, and each includes a plurality of first fuses corresponding to row address signals on a one-to-one basis. In these first fuses, row replacement addresses are programmed. The second fuse blocks are disposed for the individual memory cell blocks, and each includes a plurality of second fuses corresponding to column address signals on a one-to-one basis. In these second fuses, column replacement addresses are programmed. The selection circuits are connected to the first fuses and the second fuses to output status signals indicative of the status of either the first fuses or the second fuses. The plurality of first determination circuits receive the status signals and the address signals to determine whether or not the status signals match the address signals. The plurality of second determination circuits determine whether or not external addresses specified by the address signals match the row or column replacement addresses based on the outputs of the plurality of first determination circuits.
With the arrangement, the selection circuits output the status signals of the first fuses during the determination of row addresses, and the selection circuits output the status signals of the second fuses during the determination of column addresses. When the replacement of defective memory cells is performed in accordance with the status signals, it becomes possible to circuit-wise repair the defective memory cells using preliminarily mounted redundant memory cells.
Another example of the semiconductor memory device having the redundancy repair circuit is described in Japanese Laid-Open Patent Publication No. 2001-155493 (hereinafter the publication will be hereinafter referred to as Patent Document 2).
The semiconductor memory device includes a redundant memory circuit which stores defective row addresses. After power-on, a line for transmitting row address signals is connected to a spare row decoder circuit in accordance with the defective row address signals preliminarily stored in the redundant memory circuit, and a row decoder circuit replaced with the spare row decoder circuit is inactivated. Therefore, compared with the case where each generated row address signal is compared with defective row address signals stored in a redundant memory circuit, and a spare row decoder or a row decoder is activated in accordance with the result of the comparison, a memory cell can be accessed at a high speed.
The scale of a redundancy repair circuit in a semiconductor memory device has tended to increase for an improved yield. While the degree of integration has become higher due to fine design rules, the occupancy of the redundancy repair circuit has also become higher to cause the probability of preventing a reduction in the size of the semiconductor memory device.
However, in the semiconductor memory device described in Patent Document 1, the first and second determination circuits can be shared among the fuse blocks of the rows and columns. Therefore, compared with the case where different determination circuits are provided individually for the rows and the columns, the area of a circuit for replacement with redundant memory cells can be reduced.
However, the semiconductor memory device described in Patent Document 1 has the problem of a lower access speed because, every time a row address signal is generated, all the bits of the row address signal are compared with those of the defective row address signals stored in the redundant memory circuit, and a redundant row decoder or a row decoder is activated in accordance with the result of the comparison.
On the other hand, the semiconductor memory device described in Patent Document 2 is susceptible to an area reduction because it requires a switching circuit connected to the spare row decoder and to a row address buffer to allow the passage of only defective addresses.